1. The Field of the Invention
The present invention is generally related to a semiconductor package, and more particularly related to a structure of a substrate for a high-density semiconductor package. The present invention can be applied for making a ball grid array (BGA) package, land grid array (LGA) package or a pin grid array (PGA) package.
2. Description of the Related Art
Grid array packaging has become a technique of first choice for connecting semiconductor chips with a printed circuit board (PCB). This technology, namely, a BGA, a LGA or a PGA, is designed to make connection with a PCB. A conventional BGA, such as Amkor""s Super BGA, comprises a laminate substrate, a metal die pad attached on the laminate substrate and a semiconductor chip attached to the metal member, wherein metal member functions as a heat sink for dissipating the heat generated by the semiconductor chip. Other prior arts such as ProLinx""s Viper BGA and Substrate Technology Inc.""s Ultra BGA, comprise a build up multi-layer interconnect structure, which is directly formed on a metal panel to make the BGA substrates. These designs are generally called cavity down BGA substrates because the die is attached in a cavity on the bottom side of the metal substrate surface. However, the conventional BGA structures described above have the following problems. First, the die is usually located at a central region of the substrate and the interconnection wirings and the BGA solder balls are disposed along the perimeter of the substrate surrounding of the die and the wire bond pad areas. The BGA solder balls and wire bond pads occupy a significant lateral space on the substrate thus the substrate size becomes large in size having to accommodate the die area, the wire bond pad area and the BGA pads all on the same side. Further, larger space occupation also leads to extra consumption of material and correspondingly larger work-stations increasing the overall manufacturing cost. Furthermore, a larger substrate occupies a larger area on the printed circuit board and an increase of the corresponding product cost for the PCB which carries the substrate. Secondly, the thin film fabrication approach is used which has a high interconnect density. It results in a less number of wiring layers and a correspondingly a less amount of material usage and a shorter process cycle. This reduces the total product cost. Thirdly, since one of the primary purpose of the cavity down design is for heat dissipation, and the primary heat conduction path being through the BGA solder balls, but the BGA solder balls are disposed laterally adjacent to the die area and furthermore being isolated from the semiconductor chip by a plurality of dielectric layers, and therefore the heat conduction and heat dissipation are relatively poor. Thus the heat dissipation allowed in the semiconductor device becomes more limited.
Accordingly, it is highly desirable to improve the structure of the semiconductor package in order to resolve the above-mentioned disadvantages of the conventional semiconductor package.
According, in the light of the foregoing, it is an object of the present invention to provide a structure of a substrate for a high-density semiconductor package with the aim of resolving the problems of the prior art.
One object of the present invention is to provide a structure of a substrate for a high-density semiconductor package.
Another object of the present invention is to substantially improve the heat dissipation efficiency of the semiconductor package.
Yet another object of the present invention is to substantially reduce the size of the semiconductor chip package so that the fabrication cost of a high density package device can be reduced.
Yet another object of the present invention is to substantially reduce the space occupied by the semiconductor package on the PCB.
In accordance with the above objects and other advantages of the present invention, a structure of a substrate for a high-density semiconductor package is provided. The structure of the substrate essentially comprises a metal panel having a first surface and a second surface and an interconnect substrate attached to the second surface of the metal panel. The interconnect substrate comprises an alternately stacked interconnect wiring layers and inter-metal dielectric layers. A plurality of conductive vias is disposed within the inter-metal dielectric layers to electrically connect the wire bonding pads which are part of the first wiring layer and is next to the second surface of the metal panel. The wire bonding pads are designed for electrically connecting with of the IC chip through bondwires.
Furthermore, the first wiring layer is electrically connected to the ball pads on the bottom surface of the interconnect substrate through a plurality of wiring layers and conductive vias. The ball pads are part of the lowest wiring layer, which is furthest away from the second surface of the metal panel. The plurality of wiring layers may constitute fan out layers, power/ground layers. A conductive structure such as a solder ball may also be attached to each ball pad so that the package is electrically connected to the next level of electronic device, for example, a printed circuit board (PCB). Hence, the IC chip is capable of transmitting signals to external electronic devices through the package substrate.
The first surface of the metal panel comprises at least a die attachment area at a prescribed location for attaching an IC chip. A plurality of openings or slots are formed within the perimeter of the die attachment area at prescribed locations exposing a portion of the inter-metal dielectric layer of the interconnect substrate within the openings or slots, for example, over the buried wire bonding pads. Next, lasers may be used to selectively remove the exposed inter-metal dielectric layer until the wire bonding pads are exposed. Next, the wire bonding pads are plated with Ni/Au with an appropriate thickness. For attaching the IC chip onto the die attachment area, a layer of adhesive may be coated onto the die attachment area for the die attachment process. The IC chip pads and the Ni/Au plated wire bonding pads are bonded together using wire bonding, and thus the IC chip is electrically connected with the interconnect substrate.
Further, according to a preferred embodiment of the present invention, at least one thermally conductive via is in direct physical contact with the second surface of the metal substrate, which is positioned underneath the die attachment area. Since the thermally conductive via is directly in physical contact with the metal substrate underneath the die attachment area on which the IC chip is attached, the heat generated by the IC chip can be efficiently conducted and transferred through the thermally conductive via to the PCB. It is to be understood that the heat conduction efficiency compared to the prior art in which multiple dielectric layers are disposed between the heat sink member and the IC chip to the printed circuit board which limit the heat transfer to the printed circuit board. In this invention heat transfer is promoted by introducing the thermally conductive vias in the inter connect substrate directly in physical contact with the metal substrate underneath the die attachment area on which the IC chip is attached to the printed circuit board.
According to another aspect of the present invention, the whole second surface of the interconnect substrate is available for forming fan out layers, power/ground layers and the array of solder pads. Therefore not all of the ball grid array pads need to be routed out to the peripheral regions so that routing becomes simplified even when the semiconductor chip has a high density.
According to another aspect of the present invention, the size of the semiconductor chip package can be substantially reduced so the total length of the interconnects from the die to the edges of the package substrate can be shortened and thereby reducing the signal transmission delays. In other words, the operating speed of the device can be effectively enhanced.
According to another aspect of the present invention, the interconnect substrate is fabricated using thin-films which has a high interconnect density.
A comparatively less number of interconnect layers are needed and hence less materials are required. The cost can be substantially reduced from the material usage point of view. Further, the process is simplified and also the duration of process steps are shortened and therefore the throughput and overall fabrication cost can be effectively reduced.